Phase locked loops are disclosed, and, more particularly, charge pump circuits for reducing jitter in a phase locked loop (PLL) circuit are disclosed.
Semiconductor devices, such as a semiconductor memory device and a central processing unit (CPU), generate an internal clock signal using a clock buffer and a clock driver. However, the operating performance of these semiconductor devices deteriorate at high frequencies because the internal clock signal is delayed by a constant time period relative to an external clock signal.
As a result, an output data access time tAC (i.e., the time it takes for the data to be output after inputting the external clock signal), is longer than the generating time of the internal clock signal.
Thus, in order to reduce the performance deterioration of semiconductor devices having a long elapsing output data access time tAC, a circuit for synchronizing the internal clock signal with the external clock signal is required. The circuit for synchronizing the internal clock signal with the external clock signal is called a phase locked loop (PLL) circuit.
FIG. 1 is an internal block diagram of an ordinary prior art phase locked loop (PLL). Referring to FIG. 1, a phase locked loop 1000 includes a phase detector 100, a charge pump circuit 200, a loop filter 300, a voltage controlled oscillator (VCO) 400 and a frequency divider 500. The phase detector 100 compares a standard clock signal, which is in phase with an external clock, with an output phase of the frequency divider 500. If the output phase of the frequency divider 500 is slower than the phase of the standard clock signal, a pulse (designated as up signal (up)), is outputted from the phase detector 100 in order to increase the frequency. If the output phase of the frequency divider 500 is faster than the phase of the standard clock, a pulse (designated as down signal (down)), is outputted from the phase detector 100 in order to decrease the frequency. The charge pump circuit 200 is responsive to up or down signals received directly from the phase detector, or inverted up and down signals (/up or /down), which is the signal from the phase detector inverted by inverters 110 or 120.
A pulse output of the charge pump circuit 200 is transmitted to the loop filter 300. The filter 300 has a resistor 310 and a capacitor 320. When the down signal is transmitted to the charge pump circuit 200, an electric charge of the capacitor 320 in the loop filter 300 is reduced. When the up signal (up) is transmitted to the charge pump circuit 200, the electric charge of the capacitor 320 in the loop filter 300 is increased. The pulse output of the charge pump circuit 200 is transformed into a DC analog signal by the loop filter 200.
The voltage controlled oscillator 400 receives the DC analog signal from the loop filter 300 and outputs a constant frequency signal. The frequency divider 500 operates as a counter and divides the constant frequency signal from the voltage controlled oscillator 400 into N in order to facilitate comparison at the phase detector 100.
In the phase locked loop 1000, the phase detector 100, the charge pump circuit 200, the voltage controlled oscillator 400 and the frequency divider 500 are formed as a loop to control the phase. The number of the output frequency is N-fold increase relative to the number of the input frequency. N is set to a temporary value to get a natural multiple frequency of the input frequency.
FIG. 2A is an internal circuit diagram of a prior art charge pump circuit 200 used in FIG. 1. Referring to FIG. 2A, the internal circuit of the charge pump circuit 200 includes a first transistor MP1. An operating voltage VDD is provided through a drain of the first transistor and a bias voltage Vbiasp is applied through a gate of the first transistor for maintaining the turn-on state. The circuit 200 includes a second transistor MP2. A source of the first transistor MP1 is connected to a drain of the second transistor, and the up signal (up) is input to a gate of the second transistor. A third transistor MN2, is connected to the source of the second transistor MP2. The down signal is input to a gate of the third transistor MN2. A fourth transistor MN1 is connected to a source of the third transistor MN2. A bias voltage Vbiasn is applied to a gate of the fourth transistor MN1 for maintaining the turn-on state.
The first and second transistors MP1 and MP2 are P channel MOS transistors and the third and fourth transistors MN2 and MN1 are N channel MOS transistors. Furthermore, an output terminal OUT is connected commonly with the source of the second transistor MP2 and the drain of the third transistor MN2.
FIG. 2B is an equivalent circuit when the charge operation of the charge pump is performed by the up signal (up). FIG. 2C is an equivalent circuit when the discharge operation of the charge pump is performed by the down signal.
Referring to FIG. 2B, when the low level inverted up signal (/up) is input to the second transistor MP2, the second transistor is turned on and the operating voltage VDD applied to the drain of the first transistor MP1 is charged through the output terminal OUT because the transistor MP1 is in the turn on state.
Referring to FIG. 2C, when the high level down signal is input to the third transistor MN2, the third transistor is turned on and a charged voltage is discharged through a ground VSS because the fourth transistor MN1 is in the turn on state, and the output terminal OUT and the ground VSS are shorted.
As shown in FIG. 2B, a parasitic capacitance Cfp is generated between the operating voltage VDD and a node C. Thus, when the first transistor MP1 is changed from the turn off state to the turn on state, the potential of the node C is changed from a power potential to the output terminal OUT potential and a current Icfp flows based on such potential difference and parasitic capacitance Cfp.
Furthermore, a parasitic capacitance Cfn is generated between the ground and a node D. (See FIG. 2C). Thus, when the third transistor MN2 is changed from the turn off state to the turn on state, the node D is changed from the ground potential to the output terminal OUT potential and a current Icfn based on such potential difference and parasitic capacitance Cfn.
Therefore, a charge sharing occurs because of the parasitic capacitance so that the current supply from the output terminal OUT is unstable.
That is, overshoots occur in the output current of the charge pump circuit because of the current icfp or icfn. Thus, a jitter occurs in the voltage controlled oscillator 400, which is connected to the output terminal OUT. As a result, an error is generated in the system because the system is controlled repeatedly by the output signal of the voltage controlled oscillator 400.
This problem can be eliminated by forming the potential of nodes C and D when transistors MP2 and MN2 are in the turn off state. However, the potential of nodes C and D are identical to the potential of the output terminal OUT.
FIG. 3 is a prior art charge pump circuit 200xe2x80x2 for controlling the charge sharing when the up or down signal (up or down) are switched. Referring to FIG. 3, the charge pump circuit 200xe2x80x2 includes a first transistor MP1 (wherein an operating voltage VDD is provided through a drain and a bias voltage Vbiasp is applied through a gate for maintaining the turn-on state), a second transistor MP2 (wherein a source of the first transistor MP1 is connected and the inverted signal (/up) is input through a gate), a third transistor MP3 (wherein a source of the second transistor MP2 is connected and the up signal (up) is input through a gate), a fourth transistor MN2 (wherein a source of the second transistor MP2 is connected and the down signal is inputted through a gate), a fifth transistor MN3 (wherein a source of the third transistor MP3 is connected and the /down signal is inputted through a gate), a sixth transistor MN1 (wherein a drain is connected commonly to the source of the fourth transistor MN2 and the source of the fifth transistor MN3 and a bias voltage Vbiasn is applied through a gate for maintaining the turn-on state), and an operational amplifier A, wherein the source of the second transistor MP2 and the drain of the fourth transistor MN2 is connected commonly to a positive input terminal of the OP AMP A and the source of the third transistor MP3 and the drain of the fifth transistor MN3 is connected commonly to an inverting terminal of the OP AMP A.
The first, second and third transistors MP1, MP2 and MP3 are PMOS transistors, and the fourth, fifth and sixth transistors MN2, MN3, MN1 are NMOS transistors. Furthermore, the output terminal Vout is connected commonly to the source of the second transistor MP2, the drain of the fourth transistor MN2 and the positive input terminal of the operational amplifier A. A capacitor C1 is a phase compensating capacitance for reducing the oscillation of the operational amplifier A.
However, capacitors Cfp and Cfn are parasitic capacitance devices, which are not actual devices.
When the up or inverted up signal (up or /up) and the down or inverted down signal (down or /down) are changed, voltages of nodes N3 and N4 are identically maintained and the charge sharing from the parasitic capacitance is controlled by the operational amplifier A. As shown in FIG. 3, the operational amplifier A becomes a buffer having a voltage gain of 1 if a negative feedback operation is performed.
Hereinafter, the operation of the circuit in FIG. 3 will be described. When the inverted up signal (/up) is applied to the second transistor MP2, the second transistor MP2 is turned on and the loop filter 300 is charged. At this time, the standard voltage, which is equal to the voltage in the output terminal Vout, is applied to the negative input terminal of the operational amplifier A in order to operate as a buffer for a certain period of time.
Furthermore, the same voltage as the voltage in the output terminal Vout is applied to the node N4 by the operational amplifier A during the charge operation. The same voltage as the voltage in the output terminal Vout is maintained in the node N1 by turning on the third transistor or the fourth transistor. Also in the switching of up or inverted up signal (up or /up) and the down or inverted down signal (down or /down), overshoots by parasitic capacitors Cfp and Cfn of the charge sharing can be under control.
However, when the high level down signal is applied to the fourth transistor MN2 in the charge pump circuit 200xe2x80x2, the fourth transistor MN2 is turned on and the charged voltage in capacitors of the loop filter 300 is discharged to the ground VSS through the output terminal Vout because the sixth transistor MN1 is in the turned on state. At this time, the operational amplifier A is operated as a buffer in order to stabilize the output voltage of the output terminal Vout by minimizing the voltage change rate.
However, the charge pump circuit in FIG. 3 has the following problems. The up or inverted up signal (up or /up) and the down or inverted down signal (down or /down) are signals, which are switched continuously, and the second, third, fourth and fifth transistors MP2, MP3, MN2 and MN3 are repeatedly turned on and off by these signals. Even though the operational amplifier A is operated as the buffer, the charge sharing problem cannot be solved completely because a delay time occurs for outputting the same output voltage. Furthermore, the voltage across the third transistor MP2 cannot be always maintained at the same voltage during the charge pump operation.
Another problem is that a kickback phenomenon occurs when the up or inverted up signal (up or /up) and down or inverted down signal (down or /down) are switched at high speed. The kickback phenomenon is a phenomenon wherein the opposite voltage is induced suddenly when the voltage of some node is rapidly changed. It is because electric charges below the gate of the MOS transistor are drifted away to both directions of the transistor when the switching of the MOS transistor occurs.
A glitch, which is manifested as jitter, is generated by the kickback phenomenon. The kickback phenomenon can be solved by induction of the input as a transmission gate. However, the size of the PMOS transistor has to be 1.5 to 3 times larger than the size of the NMOS transistor in order to flow the same current. Thus, the size of the parasitic capacitor caused by the PMOS and NMOS transistors is changed so that the other problem can be addressed.
In accordance with a disclosed embodiment, a semiconductor device is provided which includes an input circuit to charge and discharge a voltage associated with an output terminal in response to a first input signal. The device also includes a dummy input circuit responsive to a second input signal to reduce jitter in the voltage associated with the output terminal. The second input signal is an inverted version of the first input signal.
In accordance with another disclosed embodiment, a charge pump circuit is provided which includes a charge circuit to develop a voltage at an output terminal in response to a first input signal. The charge pump circuit also includes a discharge circuit to discharge the voltage at the output terminal in response to a second input signal; a dummy charge responsive to a first inverted signal of the first input signal to reduce jitter; and a dummy discharge circuit responsive to a second inverted signal of the second input signal to reduce jitter.